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1/46 preliminary data november 2001 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. m36dr432c m36dr432d 32 mbit (2mb x16, dual bank, page) flash memory and 4 mbit (256k x16) sram, multiple memory product features summary n supply voltage Cv ddf =v dds =1.9v to 2.1v Cv ppf = 12v for fast program (optional) n access time: 85,100ns n low power consumption n electronic signature C manufacturer code: 20h C top device code, m36dr432c: 00a4h C bottom device code, m36dr432d: 00a5h flash memory n 32 mbit (2mb x16) boot block C parameter blocks (top or bottom location) n programming time C 10s typical C double word programming option n asyncronous page mode read C page width: 4 word C page mode access time: 35ns n dual bank operation C read within one bank while program or erase within the other C no delay between read and write operations n block protection on all blocks Cwpf for block locking n common flash interface C 64 bit security code sram n 4 mbit (256k x 16 bit) n low v dds data retention: 1v n power down features using two chip enable inputs figure 1. packages fbga stacked lfbga66 (za) 8 x 8 ball array
m36dr432c, m36dr432d 2/46 description the m36dr432 is a multichip memory device con- taining a 32 mbit boot block flash memory and a 4mbitofsram.thedeviceisofferedinastacked lfbga66 (0.8 mm pitch) package. the two components are distinguished by use with three chip enable inputs: ef for the flash memory and, e1s and e2s for the sram. the two compo- nents are also separately power supplied and grounded. figure 2. logic diagram table 1. signal names ai05522 21 a0-a20 ef dq0-dq15 m36dr432c m36dr432d gf v ssf 16 wf rpf wpf e1s e2s gs ws ubs lbs v sss v ddf v ppf v dds a0-a17 address inputs a18-a20 address inputs for flash chip only dq0-dq15 data input/output v ddf flash power supply v ppf flash optional supply voltage for fast program & erase v ssf flash ground v dds sram power supply v sss sram ground nc not connected internally flash control functions ef chip enable input gf output enable input wf write enable input rpf reset input wpf write protect input sram control functions e1s , e2s chip enable input gs output enable input ws write enable input ubs upper byte enable input lbs lower byte enable input
3/46 m36dr432c, m36dr432d figure 3. lfbga connections (top view through package) ai90204 a 8 7 6 5 4 3 2 1 e b f a12 a13 a11 a20 nc nc e2s dq12 v sss a2 a3 a6 a7 a18 ef a0 a4 nc nc dq4 ws dq15 a9 a16 dq6 dq13 nc wf a8 a10 a5 nc v ssf a17 rpf a15 a14 nc nc v ddf e1s a1 nc nc gf v dds dq7 dq5 dq14 nc v ssf nc #4 #3 c dq10 dq11 a19 wpf v ppf dq3 dq2 d dq8 dq9 gs lbs ubs dq1 dq0 g h #2 #1
m36dr432c, m36dr432d 4/46 table 2. absolute maximum ratings (1) note: 1. except for the rating "operating temperature range", stresses above those listed in the table "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant qual- ity documents. 2. minimum voltage may undershoot to C2v during transition and for less than 20ns. 3. depends on range. 4. v dd =v dds =v ddf . figure 4. functional block diagram symbol parameter value unit t a ambient operating temperature (3) C40 to 85 c t bias temperature under bias C40 to 125 c t stg storage temperature C55 to 150 c v io (2) input or output voltage C0.2 to v dd (4) +0.3 v v ddf flash chip supply voltage C0.5 to 2.7 v v dds sram chip supply voltage C0.2 to 2.6 v v ppf program voltage C0.5 to 13.0 v ai90205 flash memory 32 mbit (x16) v ssf ef gf wf rpf wpf e1s e2s gs ws ubs lbs dq0-dq15 v ddf v ppf a18-a20 a0-a17 sram 4 mbit (x16) v sss v dds
5/46 m36dr432c, m36dr432d signal descriptions see figure 2 and table 1. address inputs (a0-a17). addresses a0 to a17 are common inputs for the flash chip and the sram chip. the address inputs for the flash memory are latched during a write operation on the falling edge of the flash chip enable (ef )or write enable (wf ), while address inputs for the sram array are latched during a write operation on the falling edge of the sram chip enable lines (e1s or e2s) or write enable (ws ). address inputs (a18-a20). address a18 to a20 are address inputs for the flash chip. they are latched during a write operation on the falling edge of flash chip enable (ef ) or write enable (wf ). data input/outputs (dq0-dq15). the input is data to be programmed in the flash or sram memory array or a command to be written to the c.i. of the flash chip. both are latched on the ris- ing edge of flash chip enable (ef )orwriteen- able (wf ) and, sram chip enable lines (e1s or e2s) or write enable (ws ). the output is data from the flash memory or sram array, the elec- tronic signature manufacturer or device codes or the status register data polling bit dq7, the tog- gle bits dq6 and dq2, the error bit dq5 or the erase timer bit dq3. outputs are valid when flash chip enable (ef ) and output enable (gf )or sram chip enable lines (e1s or e2s) and output enable (gs ) are active. the output is high imped- ance when the both the flash chip and the sram chip are deselected or the outputs are disabled and when reset (rpf )isatav il . flash chip enable (ef ). the chip enable input for flash activates the memory control logic, input buffers, decoders and sense amplifiers. ef at v ih deselects the memory and reduces the power con- sumption to the standby level and output do hi-z. ef canalsobeusedtocontrolwritingtothecom- mand register and to the flash memory array, while wf remains at v il .itisnotallowedtosetef at v il ,e1s at v il and e2s at v ih at the same time. flash write enable (wf ). the write enable in- put controls writing to the command register of the flash chip and address/data latches. data are latched on the rising edge of wf . flash output enable (gf ). the output enable gates the outputs through the data buffers during a read operation of the flash chip. when gf and wf are high the outputs are high impedance. flash reset/power down input (rpf ). the rpf input provides hardware reset of the memory (without affecting the configuration register sta- tus), and/or power down functions, depending on the configuration register status. reset/power down of the memory is achieved by pulling rpf to v il for at least t plph . when the reset pulse is giv- en, if the memory is in read, erase suspend read or standby, it will output new valid data in t phq7v1 after the rising edge of rpf .ifthememoryisin erase or program modes, the operation will be aborted and the reset recovery will take a maxi- mum of t plq7v . the memory will recover from power down (when enabled) in t phq7v2 after the rising edge of rpf . see tables 1, 26 and figure 11. flash write protect (wpf ). write protect is an input to protect or unprotect the two lockable pa- rameter blocks of the flash memory. when wpf is at v il , the lockable blocks are protected. pro- gram or erase operations are not achievable. when wpf is at v ih , the lockable blocks are un- protected and they can be programmed or erased (refer to table 17). sram chip enable (e1s ,e2s). the chip en- able inputs for sram activate the memory control logic, input buffers and decoders. e1s at v ih or e2s at v il deselects the memory and reduces the power consumption to the standby level. e1s and e2s can also be used to control writing to the sram memory array, while ws remains at v il .it is not allowed to set ef at v il ,e1s at v il and e2s at v ih at the same time. sramwriteenable(ws ). the write enable in- put controls writing to the sram memory array. ws is active low. sram output enable (gs ). the output enable gates the outputs through the data buffers during a read operation of the sram chip. gs is active low. sram upper byte enable (ubs ). enable the upper bytes for sram (dq8-dq15). ubs is active low. sram lower byte enable (lbs ). enable the lower bytes for sram (dq0-dq7). lbs is active low. v ddf supply voltage (1.9v to 2.1v). flash memory power supply for all operations (read, program and erase). v ppf programming voltage (11.4v to 12.6v). used to provide high voltage for fast factory pro- gramming. high voltage on v ppf pin is required to use the double word program instruction. it is also possible to perform word program or erase in- structions with v ppf pin grounded. v dds supply voltage (1.9v to 2.1v). sram pow- er supply for all operations (read, program). v ssf and v sss ground. v ssf and v sss are the reference for all voltage measurements respec- tively in the flash and sram chips.
m36dr432c, m36dr432d 6/46 table 3. main operation modes note: x = v il or v ih ,v ppfh =12v5%. 1. if ubs and lbs are tied together the bus is at 16 bit. for an 8 bit bus configuration use ubs and lbs separately. operation mode ef gf wf rpf wpf v ppf e1s e2s gs ws ubs ,lbs (1) dq15-dq0 flash memory read v il v il v ih v ih x don't care sram must be disabled data output write v il v ih v il v ih v ih v ddf or v ppfh sram must be disabled data input block locking v il xx v ih v il don't care sram must be disabled x standby v ih xx v ih x don't care any sram mode is allowable hi-z reset x x x v il x don't care any sram mode is allowable hi-z output disable v il v ih v ih v ih x don't care any sram mode is allowable hi-z sram read flash must be disabled v il v ih v il v ih v il data out word read write flash must be disabled v il v ih v ih v il v il data in word write standby/ power down any flash mode is allowable v ih xxx x hi-z x v il x x x hi-z xxxx v ih hi-z data retention any flash mode is allowable v ih xxx x hi-z x v il x x x hi-z xxxx v ih hi-z output disable any flash mode is allowable v il v ih v ih v ih x hi-z
7/46 m36dr432c, m36dr432d flash memory component organization the flash chip is organized as 2mb x16 bits. a0- a20 are the address lines, dq0-dq15 are the data input/output. memory control is provided by chip enable ef , output enable gf and write en- able wf inputs. reset rpf is used to reset all the memory circuitry and to set the chip in power down mode if this function is enabled by a proper setting of the con- figuration register. erase and program operations are controlled by an internal program/erase con- troller (p/e.c.). status register data output on dq7 provides a data polling signal, dq6 and dq2 provide toggle signals and dq5 provides error bit to indicate the state of the p/e.c operations. memory blocks the device features asymmetrically blocked archi- tecture. the flash chip has an array of 71 blocks and is divided into two banks a and b, providing dual bank operations. while programming or erasing in bank a, read operations are possible into bank b or vice versa. the memory also fea- tures an erase suspend allowing to read or pro- gram in another block within the same bank. once suspended the erase can be resumed. the bank size and sectorization are summarized in table 4. parameter blocks are located at the top of the memory address space for the top version, and at the bottom for the bottom version. the memory maps are shown in tables 5, 6, 7 and 8. the program and erase operations are managed automatically by the p/e.c. block protection against program or erase provides additional data security. all blocks are protected at power up. in- structions are provided to protect or unprotect any block in the application. a second register locks the protection status while wpf is low (see block locking description). the reset command does not affect the configuration of unprotected blocks and the configuration register status. device operations the following operations can be performed using the appropriate bus cycles: read array (random, and page modes), write command, output dis- able, standby, reset/power down and block locking. see table 9. read. read operations are used to output the contents of the memory array, the electronic sig- nature, the status register, the cfi, the block protection status or the configuration register status. read operation of the memory array is per- formed in asynchronous page mode, that provides fast access time. data is internally read and stored in a page buffer. the page has a size of 4 words and is addressed by a0-a1 address inputs. read operations of the electronic signature, the status register, the cfi, the block protection status, the configuration register status and the security code are performed as single asynchronous read cycles (random read). both chip enable ef and output enable gf must be at v il in order to read the output of the memory. write. write operations are used to give instruc- tion commands to the memory or to latch input data to be programmed. a write operation is initi- ated when chip enable ef and write enable wf are at v il with output enable gf at v ih .address- es are latched on the falling edge of wf or ef whichever occurs last. commands and input data are latched on the rising edge of wf or ef which- ever occurs first. noise pulses of less than 5ns typ- ical on ef ,wf and gf signals do not start a write cycle. dual bank operations. the dual bank allows to read data from one bank of memory while a pro- gram or erase operation is in progress in the other bank of the memory. read and write cycles can be initiated for simultaneous operations in different banks without any delay. status register during program or erase must be monitored using an ad- dress within the bank being modified. output disable. the data outputs are high im- pedance when the output enable gf is at v ih with write enable wf at v ih . standby. the memory is in standby when chip enable ef is at v ih and the p/e.c. is idle. the power consumption is reduced to the standby level and the outputs are high impedance, independent of the output enable gf or write enable wf in- puts. automatic standby. when in read mode, after 150ns of bus inactivity and when cmos levels are driving the addresses, the chip automatically en- ters a pseudo-standby mode where consumption is reduced to the cmos standby value, while out- puts still drive the bus. power down. the memory is in power down when the configuration register is set for power down and rpf is at v il . the power consumption is reduced to the power down level, and outputs are in high impedance, independent of the chip enable ef , output enable gf or write enable wf inputs. block locking. any combination of blocks can be temporarily protected against program or erase by setting the lock register and pulling wpf to v il (see block lock instruction).
m36dr432c, m36dr432d 8/46 table4.banksizeandsectorization table 5. bank a, top boot block addresses m36dr432c table 6. bank b, top boot block addresses m36dr432c bank size parameter blocks main blocks bank a 8 mbit 8 blocks of 4 kword 15 blocks of 32 kword bank b 24 mbit - 48 blocks of 32 kword # size (kword) address range 22 4 1ff000h-1fffffh 21 4 1fe000h-1fefffh 20 4 1fd000h-1fdfffh 19 4 1fc000h-1fcfffh 18 4 1fb000h-1fbfffh 17 4 1fa000h-1fafffh 16 4 1f9000h-1f9fffh 15 4 1f8000h-1f8fffh 14 32 1f0000h-1f7fffh 13 32 1e8000h-1effffh 12 32 1e0000h-1e7fffh 11 32 1d8000h-1dffffh 10 32 1d0000h-1d7fffh 9 32 1c8000h-1cffffh 8 32 1c0000h-1c7fffh 7 32 1b8000h-1bffffh 6 32 1b0000h-1b7fffh 5 32 1a8000h-1affffh 4 32 1a0000h-1a7fffh 3 32 198000h-19ffffh 2 32 190000h-197fffh 1 32 188000h-18ffffh 0 32 180000h-187fffh # size (kword) address range 47 32 178000h-17ffffh 46 32 170000h-177fffh 45 32 168000h-16ffffh 44 32 160000h-167fffh 43 32 158000h-15ffffh 42 32 150000h-157fffh 41 32 148000h-14ffffh 40 32 140000h-147fffh 39 32 138000h-13ffffh 38 32 130000h-137fffh 37 32 128000h-12ffffh 36 32 120000h-127fffh 35 32 118000h-11ffffh 34 32 110000h-117fffh 33 32 108000h-10ffffh 32 32 100000h-107fffh 31 32 0f8000h-0fffffh 30 32 0f0000h-0f7fffh 29 32 0e8000h-0effffh 28 32 0e0000h-0e7fffh 27 32 0d8000h-0dffffh 26 32 0d0000h-0d7fffh 25 32 0c8000h-0cffffh 24 32 0c0000h-0c7fffh 23 32 0b8000h-0bffffh 22 32 0b0000h-0b7fffh 21 32 0a8000h-0affffh 20 32 0a0000h-0a7fffh 19 32 098000h-09ffffh 18 32 090000h-097fffh 17 32 088000h-08ffffh 16 32 080000h-087fffh 15 32 078000h-07ffffh 14 32 070000h-077fffh 13 32 068000h-06ffffh 12 32 060000h-067fffh 11 32 058000h-05ffffh 10 32 050000h-057fffh 9 32 048000h-04ffffh 8 32 040000h-047fffh 7 32 038000h-03ffffh 6 32 030000h-037fffh 5 32 028000h-02ffffh 4 32 020000h-027fffh 3 32 018000h-01ffffh 2 32 010000h-017fffh 1 32 008000h-00ffffh 0 32 000000h-007fffh
9/46 m36dr432c, m36dr432d table 7. bank b, bottom boot block addresses m36dr432d table 8. bank a, bottom boot block addresses m36dr432d # size (kword) address range 47 32 1f8000h-1fffffh 46 32 1f0000h-1f7fffh 45 32 1e8000h-1effffh 44 32 1e0000h-1e7fffh 43 32 1d8000h-1dffffh 42 32 1d0000h-1d7fffh 41 32 1c8000h-1cffffh 40 32 1c0000h-1c7fffh 39 32 1b8000h-1bffffh 38 32 1b0000h-1b7fffh 37 32 1a8000h-1affffh 36 32 1a0000h-1a7fffh 35 32 198000h-19ffffh 34 32 190000h-197fffh 33 32 188000h-18ffffh 32 32 180000h-187fffh 31 32 178000h-17ffffh 30 32 170000h-177fffh 29 32 168000h-16ffffh 28 32 160000h-167fffh 27 32 158000h-15ffffh 26 32 150000h-157fffh 25 32 148000h-14ffffh 24 32 140000h-147fffh 23 32 138000h-13ffffh 22 32 130000h-137fffh 21 32 128000h-12ffffh 20 32 120000h-127fffh 19 32 118000h-11ffffh 18 32 110000h-117fffh 17 32 108000h-10ffffh 16 32 100000h-107fffh 15 32 0f8000h-0fffffh 14 32 0f0000h-0f7fffh 13 32 0e8000h-0effffh 12 32 0e0000h-0e7fffh 11 32 0d8000h-0dffffh 10 32 0d0000h-0d7fffh 9 32 0c8000h-0cffffh 8 32 0c0000h-0c7fffh 7 32 0b8000h-0bffffh 6 32 0b0000h-0b7fffh 5 32 0a8000h-0affffh 4 32 0a0000h-0a7fffh 3 32 098000h-09ffffh 2 32 090000h-097fffh 1 32 088000h-08ffffh 0 32 080000h-087fffh # size (kword) address range 22 32 078000h-07ffffh 21 32 070000h-077fffh 20 32 068000h-06ffffh 19 32 060000h-067fffh 18 32 058000h-05ffffh 17 32 050000h-057fffh 16 32 048000h-04ffffh 15 32 040000h-047fffh 14 32 038000h-03ffffh 13 32 030000h-037fffh 12 32 028000h-02ffffh 11 32 020000h-027fffh 10 32 018000h-01ffffh 9 32 010000h-017fffh 8 32 008000h-00ffffh 7 4 007000h-007fffh 6 4 006000h-006fffh 5 4 005000h-005fffh 4 4 004000h-004fffh 3 4 003000h-003fffh 2 4 002000h-002fffh 1 4 001000h-001fffh 0 4 000000h-000fffh
m36dr432c, m36dr432d 10/46 table 9. user bus operations (1) note: 1. x = don't care. table 10. read electronic signature (as and read cfi instructions) note: 1. t.b.a. to be announced. table 11. read block protection (as and read cfi instructions) table 12. read configuration register (as and read cfi instructions) operation ef gf wf rpf wpf dq0-dq15 write v il v ih v il v ih v ih data input output disable v il v ih v ih v ih v ih hi-z standby v ih xx v ih v ih hi-z reset / power down x x x v il v ih hi-z block locking v il xx v ih v il x code device ef gf wf a0 a1 a2-a7 other addresses dq0-dq7 dq8-dq15 manufacturer code v il v il v ih v il v il 0 don't care 20h 00h device code m36dr432c v il v il v ih v ih v il 0 don't care t.b.a. (1) t.b.a. (1) m36dr432d v il v il v ih v ih v il 0 don't care t.b.a. (1) t.b.a. (1) block status ef gf wf a0 a1 a2-a7 other addresses a12-a20 dq0 dq1 dq2-dq15 protected block v il v il v ih v il v ih 0 don't care block address 1 0 0000h unprotected block v il v il v ih v il v ih 0 don't care block address 0 0 0000h locked block v il v il v ih v il v ih 0 don't care block address x 1 0000h rpf function ef gf wf a0 a1 a2-a7 other addresses dq10 dq0-dq9 dq11-dq15 reset v il v il v ih v ih v ih 0 don't care 0 don't care reset/power down v il v il v ih v ih v ih 0 don't care 1 don't care
11/46 m36dr432c, m36dr432d instructions and commands seventeen instructions are defined (see table 15), and the internal p/e.c. automatically handles all timing and verification of the program and erase operations. the status register data poll- ing, toggle, error bits can be read at any time, dur- ing programming or erase, to monitor the progress of the operation. instructions, made up of one or more commands writtenincycles,canbegiventotheprogram/ erase controller through a command interface (c.i.). the c.i. latches commands written to the memory. commands are made of address and data sequences. two coded cycles unlock the command interface. they are followed by an input command or a confirmation command. the coded sequence consists of writing the data aah at the address 555h during the first cycle and the data 55h at the address 2aah during the second cycle. instructions are composed of up to six cycles. the first two cycles input a coded sequence to the command interface which is common to all in- structions (see table 15). the third cycle inputs the instruction set-up command. subsequent cy- cles output the addressed data, electronic signa- ture, block protection, configuration register status or cfi query for read operations. in order to give additional data protection, the instructions for block erase and bank erase require further command inputs. for a program instruction, the fourth command cycle inputs the address and data to be programmed. for a double word program- ming instruction, the fourth and fifth command cy- cles input the address and data to be programmed. for a block erase and bank erase instructions, the fourth and fifth cycles input a fur- ther coded sequence before the erase confirm command on the sixth cycle. any combination of blocks of the same memory bank can be erased. erasure of a memory block may be suspended, in order to read data from another block or to pro- gram data in another block, and then resumed. when power is first applied the command interface is reset to read array. command sequencing must be followed exactly. any invalid combination of commands will reset the device to read array. the increased number of cycles has been chosen to ensure maximum data security. table 13. commands read/reset (rd) instruction. the read/reset instruction consists of one write cycle giving the command f0h. it can be optionally preceded by the two coded cycles. subsequent read opera- tions will read the memory array addressed and output the data read. cfi query (rcfi) instruction. common flash interface query mode is entered writing 98h at ad- dress 55h. the cfi data structure gives informa- tion on the device, such as the sectorization, the command set and some electrical specifications. table 18, 19, 20 and 21 show the addresses used to retrieve each data. the cfi data structure con- tains also a security area; in this section, a 64 bit unique security number is written, starting at ad- dress 80h. this area can be accessed only in read mode by the final user and there are no ways of changing the code after it has been written by st. write a read instruction (rd) to return to read mode. auto select (as) instruction. this instruction uses two coded cycles followed by one write cycle giv- ing the command 90h to address 555h for com- mand set-up. a subsequent read will output the manufacturer or the device code (electronic sig- nature), the block protection status or the config- uration register status depending on the levels of a0 and a1 (see table 10, 11 and 12). a7-a2 must be at v il , while other address input are ignored. hex code command 00h bypass reset 10h bank erase confirm 20h unlock bypass 30h block erase resume/confirm 40h double word program 60h block protect, or block unprotect, or block lock, or write configuration register 80h set-up erase 90h read electronic signature, or block protection status, or configuration register status 98h cfi query a0h program b0h erase suspend f0h read array/reset
m36dr432c, m36dr432d 12/46 the bank address is dont care for this instruction. the electronic signature can be read from the memory allowing programming equipment or ap- plications to automatically match their interface to the characteristics of flash chip. the manufactur- er code is output when the address lines a0 and a1 are at v il , the device code is output when a0 is at v ih with a1 at v il . the codes are output on dq0-dq7 with dq8- dq15 at 00h. the as instruction also allows the access to the block protection status. after giving the as instruction, a0 is set to v il with a1 at v ih , while a12-a20 define the address of the block to be verified. a read in these conditions will output a 01h if the block is protected and a 00h if the block is not protected. the as instruction finally allows the access to the configuration register status if both a0 and a1 are set to v ih . if dq10 is '0' only the reset function is active as rpf is set to v il (default at power-up). if dq10 is '1' both the reset and the power down functions will be achieved by pulling rpf to v il . the other bits of the configuration register are re- served and must be ignored. a reset command puts the device in read array mode. write configuration register (cr) instruc- tion. this instruction uses two coded cycles fol- lowed by one write cycle giving the command 60h to address 555h. a further write cycle giving the command 03h writes the contents of address bits a0-a15 to the 16 bits configuration register. bits written by inputs a0-a9 and a11-a15 are reserved for future use. address input a10 defines the sta- tus of the reset/power down functions. it must be set to v il to enable only the reset function and to v ih to enable also the power down function. at power up all the configuration register bits are reset to '0'. enter bypass mode (eby) instruction. this in- struction uses the two coded cycles followed by one write cycle giving the command 20h to ad- dress 555h for mode set-up. once in bypass mode, the device will accept the exit bypass (xby) and program or double word program in bypass mode (pgby, dpgby) commands. the bypass mode allows to reduce the overall pro- gramming time when large memory arrays need to be programmed. exit bypass mode (xby) instruction. this in- struction uses two write cycles. the first inputs to the memory the command 90h and the second in- puts the exit bypass mode confirm (00h). after the xby instruction, the device resets to read memo- ry array mode. program in bypass mode (pgby) instruc- tion. this instruction uses two write cycles. the program command a0h is written to any address on the first cycle and the second write cycle latch- es the address on the falling edge of wf or ef and the data to be written on the rising edge and starts the p/e.c. read operations within the same bank output the status register bits after the program- ming has started. memory programming is made only by writing '0' in place of '1'. status bits dq6 and dq7 determine if programming is on-going and dq5 allows verification of any possible error. program (pg) instruction. this instruction uses four write cycles. the program command a0h is written to address 555h on the third cycle after two coded cycles. a fourth write operation latches the address and the data to be written and starts the p/e.c. read operations within the same bank out- put the status register bits after the programming has started. memory programming is made only by writing '0' in place of '1'. status bits dq6 and dq7 determine if programming is on-going and dq5 allows verification of any possible error. pro- gramming at an address not in blocks being erased is also possible during erase suspend. double word program (dpg) instruction. this feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel. high voltage (11.4v to 12.6v) on v pp pin is required. this instruction uses five write cy- cles. the double word program command 40h is written to address 555h on the third cycle after two coded cycles. a fourth write cycle latches the ad- dress and data to be written to the first location. a fifth write cycle latches the new data to be written to the second location and starts the p/e.c.. note that the two locations must have the same address except for the address bit a0. the double word program can be executed in bypass mode (dpg- by) to skip the two coded cycles at the beginning of each command. block protect (bp), block unprotect (bu), block lock (bl) instructions. all blocks are protected at power-up. each block of the array has two levels of protection against program or erase operation. the first level is set by the block protect instruction; a protected block cannot be pro- grammed or erased until a block unprotect in- struction is given for that block. a second level of protection is set by the block lock instruction, and requires the use of the wpf pin, according to the following scheme: C when wpf is at v ih , the lock status is overrid- den and all blocks can be protected or unpro- tected; C when wpf is at v il , lock status is enabled; the locked blocks are protected, regardless of their previous protect state, and protection status cannot be changed. blocks that are not locked can still change their protection status, and pro- gram or erase accordingly;
13/46 m36dr432c, m36dr432d C the lock status is cleared for all blocks at power up; once a block has been locked state can be cleared only with a reset command. the protec- tion and lock status can be monitored for each block using the autoselect (as) instruction. pro- tected blocks will output a 1 on dq0 and locked blocks will output a 1 on dq1. refer to table 14 for a list of the protection states. block erase (be) instruction. this instruction uses a minimum of six write cycles. the erase set-up command 80h is written to address 555h on third cycle after the two coded cycles. the block erase confirm command 30h is similarly written on the sixth cycle after another two coded cycles and an address within the block to be erased is given and latched into the memory. additional block erase confirm commands and block addresses can be written subsequently to erase other blocks in parallel, without further cod- ed cycles. all blocks must belong to the same bank of memory; if a new block belonging to the other bank is given, the operation is aborted. the erase will start after an erase timeout period of 100s. thus, additional erase confirm commands for other blocks must be given within this delay. the input of a new erase confirm command will restart the timeout period. the status of the inter- nal timer can be monitored through the level of dq3, if dq3 is '0' the block erase command has been given and the timeout is running, if dq3 is '1', the timeout has expired and the p/e.c. is erasing the block(s). if the second command given is not an erase confirm or if the coded cycles are wrong, the instruction aborts, and the device is reset to read array. it is not necessary to program the block with 00h as the p/e.c. will do this automati- cally before erasing to ffh. read operations with- in the same bank, after the sixth rising edge of wf or ef , output the status register bits. during the execution of the erase by the p/e.c., the memory accepts only the erase suspend es instruction; the read/reset rd instruction is ac- cepted during the 100s time-out period. data polling bit dq7 returns '0' while the erasure is in progress and '1' when it has completed. the tog- gle bit dq6 toggles during the erase operation, and stops when erase is completed. after completion the status register bit dq5 re- turns '1' if there has been an erase failure. in such a situation, the toggle bit dq2 can be used to de- termine which block is not correctly erased. in the case of erase failure, a read/reset rd instruction is necessary in order to reset the p/e.c. bank erase (bke) instruction. this instruction uses six write cycles and is used to erase all the blocks belonging to the selected bank. the erase set-up command 80h is written to address 555h on the third cycle after the two coded cycles. the bank erase confirm command 10h is similarly written on the sixth cycle after another two coded cycles at an address within the selected bank. if the second command given is not an erase con- firm or if the coded cycles are wrong, the instruc- tion aborts and the device is reset to read array. it is not necessary to program the array with 00h first as the p/e.c. will automatically do this before erasing it to ffh. read operations within the same bank after the sixth rising edge of wf or ef output the status register bits. during the execution of the erase by the p/e.c., data polling bit dq7 re- turns '0', then '1' on completion. the toggle bit dq6 toggles during erase operation and stops when erase is completed. after completion the status register bit dq5 returns '1' if there has been an erase failure. erase suspend (es) instruction. in a dual bank memory the erase suspend instruction is used to read data within the bank where erase is in progress. it is also possible to program data in blocks not being erased. the erase suspend instruction consists of writing the command b0h without any specific address. no coded cycles are required. erase suspend is accepted only during the block erase instruction execution. the toggle bit dq6 stops toggling when the p/e.c. is suspended within 15s after the erase suspend (es) command has been writ- ten. the device will then automatically be set to read memory array mode. when erase is sus- pended, a read from blocks being erased will out- put dq2 toggling and dq6 at '1'. a read from a block not being erased returns valid data. during suspension the memory will respond only to the erase resume er and the program pg instruc- tions. a program operation can be initiated during erase suspend in one of the blocks not being erased. it will result in dq6 toggling when the data is being programmed. erase resume (er) instruction. if an erase suspend instruction was previously executed, the erase operation may be resumed by giving the command 30h, at an address within the bank be- ing erased and without any coded cycle.
m36dr432c, m36dr432d 14/46 table 14. protection states (1) note: 1. all blocks are protected at power-up, so the default configuration is 001 or 101 according to wpf status. 2. current state and next state gives the protection status of a block. the protection status is defined by the write protect pin and by dq1(=1foralockedblock)anddq0(=1foraprotectedblock)asreadintheautoselectinstructionwitha1=v ih anda0=v il . 3. next state is the protection status of a block after a protect or unprotect or lock command has been issued or after wpf has changed its logic value. 4. a wpf transition to v ih on a locked block will restore the previous dq0 value, giving a 111 or 110. table 15. instructions (1,2) current state (2) (wp , dq1, dq0) program/erase allowed next state after event (3) protect unprotect lock wp transition 100 yes 101 100 111 000 101 no 101 100 111 001 110 ye s 111 110 111 011 111 no 111 110 111 011 000 yes 001 000 011 100 001 no 001 000 011 101 011 no 011 011 011 111 or 110 (4) mne. instr. cyc. 1st cyc. 2nd cyc. 3rd cyc. 4th cyc. 5th cyc. 6th cyc. rd (4) read/reset memory array 1+ addr. (3) x read memory array until a new write cycle is initiated. data f0h 3+ addr. 555h 2aah 555h read memory array until a new write cycle is initiated. data aah 55h f0h rcfi cfi query 1+ addr. 55h read cfi data until a new write cycle is initiated. data 98h as (4) auto select 3+ addr. 555h 2aah 555h read electronic signature or block protection or configuration register status until a new cycle is initiated. data aah 55h 90h cr configuration register write 4 addr. 555h 2aah 555h configura- tion data data aah 55h 60h 03h pg program 4 addr. 555h 2aah 555h program address read data polling or toggle bit until program completes. data aah 55h a0h program data dpg double word program 5 addr. 555h 2aah 555h program address 1 program address 2 note 6, 7 data aah 55h 40h program data 1 program data 2 eby enter bypass mode 3 addr. 555h 2aah 555h data aah 55h 20h
15/46 m36dr432c, m36dr432d note: 1. commands not interpreted in this table will default to read array mode. 2. for coded cycles address inputs a11-a20 are don't care. 3. x = don't care. 4. the first cycles of the rd or as instructions are followed by read operations. any number of read cycles can occur after the com- mand cycles. 5. during erase suspend, read and data program functions are allowed in blocks not being erased. 6. program address 1 and program address 2 must be consecutive addresses differing only for address bit a0. 7. high voltage on v ppf (11.4v to 12.6v) is required for the proper execution of the double word program instruction. xby exit bypass mode 2 addr. xx data 90h 00h pgby program in bypass mode 2 addr. x program address read data polling or toggle bit until program completes. data a0h program data dpgby double word program in bypass mode 3 addr. x program address 1 program address 2 note 6, 7 data 40h program data 1 program data 2 bp block protect 4 addr. 555h 2aah 555h block address data aah 55h 60h 01h bu block unprotect 1 addr. 555h 2aah 555h block address data aah 55h 60h d0h bl block lock 4 addr. 555h 2aah 555h block address data aah 55h 60h 2fh be block erase 6+ addr. 555h 2aah 555h 555h 2aah block address data aah 55h 80h aah 55h 30h bke bank erase 6 addr. 555h 2aah 555h 555h 2aah bank address data aah 55h 80h aah 55h 10h es erase suspend 1 addr. (3) x read until toggle stops, then read all the data needed from any blocks not being erased then resume erase. data b0h er erase resume 1 addr. bank address read data polling or toggle bits until erase completes or erase is suspended another time data 30h mne. instr. cyc. 1st cyc. 2nd cyc. 3rd cyc. 4th cyc. 5th cyc. 6th cyc.
m36dr432c, m36dr432d 16/46 status register bits p/e.c. status is indicated during execution by data polling on dq7, detection of toggle on dq6 and dq2, or error on dq5 bits. any read attempt within the bank being modified and during program or erase command execution will automatically out- put these five status register bits. the p/e.c. au- tomatically sets bits dq2, dq5, dq6 and dq7. other bits (dq0, dq1 and dq4) are reserved for future use and should be masked (see tables 17 and 16). read attempts within the bank not being modified will output array data. data polling bit (dq7). when programming op- erations are in progress, this bit outputs the com- plement of the bit being programmed on dq7. in case of a double word program operation, the complement is done on dq7 of the last word writ- ten to the command interface, i.e. the data written in the fifth cycle. during erase operation, it outputs a '0'. after completion of the operation, dq7 will output the bit last programmed or a '1' after eras- ing. data polling is valid and only effective during p/e.c. operation, that is after the fourth wf pulse for programming or after the sixth wf pulse for erase. it must be performed at the address being programmed or at an address within the block be- ing erased. see figure 25 for the data polling flowchart and figure 12 for the data polling wave- forms. dq7 will also flag the erase suspend mode by switching from '0' to '1' at the start of the erase suspend. in order to monitor dq7 in the erase suspend mode an address within a block being erased must be provided. for a read operation in suspend mode, dq7 will output '1' if the read is at- tempted on a block being erased and the data val- ue on other blocks. during program operation in erase suspend mode, dq7 will have the same be- havior as in the normal program execution outside of the suspend mode. toggle bit (dq6). when programming or eras- ing operations are in progress, successive at- tempts to read dq6 will output complementary data. dq6 will toggle following toggling of either gf ,oref when gf is at v il . the operation is com- pleted when two successive reads yield the same output data. the next read will output the bit last programmed or a '1' after erasing. the toggle bit dq6 is valid only during p/e.c. operations, that is after the fourth wf pulse for programming or after the sixth wf pulse for erase. dq6 will be set to '1' if a read operation is attempted on an erase sus- pend block. when erase is suspended dq6 will toggle during programming operations in a block different from the block in erase suspend. either ef or gf toggling will cause dq6 to toggle. see figure 25 for toggle bit flowchart and figure 13 for toggle bit waveforms. toggle bit (dq2). this toggle bit, together with dq6, can be used to determine the device status during the erase operations. during erase sus- pend a read from a block being erased will cause dq2 to toggle. a read from a block not being erased will output data. dq2 will be set to '1' during program operation and to 0 in erase operation. after erase completion and if the error bit dq5 is set to '1', dq2 will toggle if the faulty block is ad- dressed. error bit (dq5). this bit is set to '1' by the p/e.c. when there is a failure of programming or block erase, that results in invalid data in the memory block. in case of an error in block erase or pro- gram, the block in which the error occurred or to which the programmed data belongs, must be dis- carded. other blocks may still be used. the error bit resets after a read/reset (rd) instruction. in case of success of program or erase, the error bit will be set to '0'. erase timer bit (dq3). this bit is set to 0 by the p/e.c. when the last block erase command has been entered to the command interface and it is awaiting the erase start. when the erase timeout period is finished, dq3 returns to 1, in the range of 80s to 120s. table 16. polling and toggle bits mode dq7 dq6 dq2 program dq7 toggle 1 erase 0 toggle n/a erase suspend read (in erase suspend block) 1 1 toggle erase suspend read (outside erase suspend block) dq7 dq6 dq2 erase suspend program dq7 toggle 1
17/46 m36dr432c, m36dr432d table 17. status register bits (1) note: 1. logic level '1' is high, '0' is low. -0-1-0-0-0-1-1-1-0- represent bit value in successive read operations. 2. in case of double word program dq7 refers to the last word input. dq name logic level definition note 7 data polling '1' erase complete or erase block in erase suspend. indicates the p/e.c. status, check during program or erase, and on completion before checking bits dq5 for program or erase success. '0' erase on-going dq program complete or data of non erase block during erase suspend. dq program on-going (2) 6 toggle bit '-1-0-1-0-1-0-1-' erase or program on-going successive reads output complementary data on dq6 while programming or erase operations are on-going. dq6 remains at constant level when p/e.c. operations are completed or erase suspend is acknowledged. dq program complete '-1-1-1-1-1-1-1-' erase complete or erase suspend on currently addressed block 5 error bit '1' program or erase error this bit is set to '1' in the case of programming or erase failure. '0' program or erase on-going 4 reserved 3 erase time bit '1' erase timeout period expired p/e.c. erase operation has started. only possible command entry is erase suspend (es) '0' erase timeout period on-going an additional block to be erased in parallel can be entered to the p/e.c: 2 toggle bit '-1-0-1-0-1-0-1-' erase suspend read in the erase suspended block. erase error due to the currently addressed block (when dq5 = '1'). indicates the erase status and allows to identify the erased block. 1 program on-going or erase complete. dq erase suspend read on non erase suspend block. 1 reserved 0 reserved
m36dr432c, m36dr432d 18/46 power consumption power down the memory provides reset/power down control input rpf . the power down function can be acti- vated only if the relevant configuration register bit is set to '1'. in this case, when the rpf signal is pulled at v ss the supply current drops to typically i cc2 (see table 24), the memory is deselected and the outputs are in high impedance.if rpf is pulled to v ss during a program or erase operation, this operation is aborted in t plq7v and the memory content is no longer valid (see reset/power down input description). power up the memory command interface is reset on pow- er-uptoreadarray.eitheref or wf must be tied to v ih during power-up to allow maximum security and the possibility to write a command on the first rising edge of wf . during power-up rpf must remain low for at least 50s after v dd is applied, to allow correct initializa- tion of the cpu. supply rails normal precautions must be taken for supply volt- age decoupling; each device in a system should have the v ddf rails decoupled with a 0.1f capac- itorclosetothev ddf and v ss pins. the pcb trace widths should be sufficient to carry the required v ddf program and erase currents.
19/46 m36dr432c, m36dr432d common flash interface (cfi) the common flash interface (cfi) specification is a jedec approved, standardised data structure that can be read from the flash memory device. cfi allows a system software to query the flash device to determine various electrical and timing parameters, density information and functions supported by the device. cfi allows the system to easily interface to the flash memory, to learn about its features and parameters, enabling the software to configure itself when necessary. tables 18, 19, 20, and 21 show the address used to retrieve each data. the cfi data structure gives information on the device, such as the sectorization, the command set and some electrical specifications. tables 18, 19, 20, and 21 show the addresses used to re- trieve each data. the cfi data structure contains also a security area; in this section, a 64 bit unique security number is written, starting at address 81h. this area can be accessed only in read mode and there are no ways of changing the code after it has been written by st. write a read instruction to re- turn to read mode. refer to the cfi query instruc- tion to understand how the m36dr432 enters the cfi query mode. table 18. query structure overview note: the flash memory display the cfi data structure when cfi query command is issued. in this table are listed the main sub-sections detailed in tables 19, 20 and 21. query data are always presented on the lowest order data outputs. table 19. cfi query identification string note: 1. query data are always presented on the lowest - order data outputs (dq7-dq0) only. dq8-dq15 are 0. 2. t.b.a. to be announced. offset sub-section name description 00h reserved reserved for algorithm-specific information 10h cfi query identification string command set id and algorithm data offset 1bh system interface information device timing & voltage information 27h device geometry definition flash device layout p primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) a alternate algorithm-specific extended query table additional information specific to the alternate algorithm (optional) offset data description 00h 0020h manufacturer code 01h t.b.a. (2) device code 02h-0fh reserved reserved 10h 0051h query unique ascii string "qry" 11h 0052h query unique ascii string "qry" 12h 0059h query unique ascii string "qry" 13h 0002h primary algorithm command set and control interface id code 16 bit id code defining a specific algorithm 14h 0000h 15h offset = p = 0040h address for primary algorithm extended query table 16h 0000h 17h 0000h alternate vendor command set and control interface id code second vendor - specified algorithm supported (note: 0000h means none exists) 18h 0000h 19h value = a = 0000h address for alternate algorithm extended query table note: 0000h means none exists 1ah 0000h
m36dr432c, m36dr432d 20/46 table 20. cfi query system interface information offset data description 1bh 0017h v ddf logic supply minimum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 millivolts 1ch 0022h v ddf logic supply maximum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 millivolts 1dh 0000h v ppf [programming] supply minimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 millivolts note: this value must be 0000h if no v pp pin is present 1eh 00c0h v ppf [programming] supply maximum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 millivolts note: this value must be 0000h if no v pp pin is present 1fh 0004h typical timeout per single byte/word program (multi-byte program count = 1), 2 n s (if supported; 0000h = not supported) 20h 0000h typical timeout for maximum-size multi-byte program or page write, 2 n s (if supported; 0000h = not supported) 21h 000ah typical timeout per individual block erase, 2 n ms (if supported; 0000h = not supported) 22h 0000h typical timeout for full chip erase, 2 n ms (if supported; 0000h = not supported) 23h 0004h maximum timeout for byte/word program, 2 n times typical (offset 1fh) (0000h = not supported) 24h 0000h maximum timeout for multi-byte program or page write, 2 n times typical (offset 20h) (0000h = not supported) 25h 0004h maximum timeout per individual block erase, 2 n times typical (offset 21h) (0000h = not supported) 26h 0000h maximum timeout for chip erase, 2 n times typical (offset 22h) (0000h = not supported)
21/46 m36dr432c, m36dr432d table 21. device geometry definition offset word mode data description 27h 0016h device size = 2 n in number of bytes 28h 0001h flash device interface code description: asynchronous x16 29h 0000h 2ah 0000h maximum number of bytes in multi-byte program or page = 2 n 2bh 0000h 2ch 0002h number of erase block regions within device bit 7 to 0 = x = number of erase block regions note:1. x = 0 means no erase blocking, i.e. the device erases at once in "bulk." 2. x specifies the number of regions within the device containing one or more con- tiguous erase blocks of the same size. for example, a 128kb device (1mb) having blocking of 16kb, 8kb, four 2kb, two 16kb, and one 64kb is considered to have 5 erase block regions. even though two regions both contain 16kb blocks, the fact that they are not contiguous means they are separate erase block regions. 3. by definition, symmetrically block devices have only one blocking region. m36dr432c m36dr432c erase block region information bit 31 to 16 = z, where the erase block(s) within this region are (z) times 256 bytes in size. the value z = 0 is used for 128 byte block size. e.g. for 64kb block size, z = 0100h = 256 => 256 * 256 = 64k bit 15 to 0 = y, where y+1 = number of erase blocks of identical size within the erase block region: e.g. y = d15-d0 = ffffh => y+1 = 64k blocks [maximum number] y = 0 means no blocking (# blocks = y+1 = "1 block") note: y = 0 value must be used with number of block regions of one as indicated by (x) = 0 2dh 003eh 2eh 0000h 2fh 0000h 30h 0001h 31h 0007h 32h 0000h 33h 0020h 34h 0000h m36dr432d m36dr432d 2dh 0007h 2eh 0000h 2fh 0020h 30h 0000h 31h 003eh 32h 0000h 33h 0000h 34h 0001h
m36dr432c, m36dr432d 22/46 sram component device operations the following operations can be performed using the appropriate bus cycles: read array, write ar- ray, output disable, power down (see table 3). read. read operations are used to output the contents of the sram array. the sram is in read mode whenever write enable (ws )isatv ih with output enable (gs )atv il , and both chip enables (e1s and e2s) and ubs ,lbs combinations are asserted. valid data will be available at the output pins within t avqv after the last stable address, providing gs is low, e1s is low and e2s is high. if chip enable or output enable access times are not met, data access will be measured from the limiting parame- ter (t e1lqv ,t e2hqv ,ort glqv ) rather than the ad- dress. data out may be indeterminate at t e1lqx , t e2hqx and t glqx , but data lines will always be val- id at t av q v (see table 31, figures 16 and 17). write. write operations are used to write data in the sram. the sram is in write mode whenever the ws and e1s pins are at v il , with e2s at v ih . either the chip enable inputs (e1s and e2s) or the write enable input (ws ) must be de-asserted during address transitions for subsequent write cy- cles. write begins with the concurrence of both chip enables being active with ws at v il .awrite begins at the latest transition among e1s going to v il ,e2sgoingtov ih and ws going to v il . there- fore, address setup time is referenced to write en- able and both chip enables as t avwl ,t ave1l and t ave2h respectively, and is determined by the latter occurring edge. the write cycle can be terminated bytherisingedgeofe1s , the rising edge of ws or the falling edge of e2s, whichever occurs first. if the output is enabled (e1s =v il ,e2s=v ih and gs =v il ), then ws will return the outputs to high impedance within t wlqz of its falling edge. care must be taken to avoid bus contention in this type of operation. data input must be valid for t dvwh before the rising edge of write enable, or for t dve1h before the rising edge of e1s or for t dve2l before the falling edge of e2s, whichever occurs first, and remain valid for t whdx ,t e1hax or t e2lax (see table 32, figure 19, 21, 23). standby/power-down. the sram chip has a chip enable power-down feature which invokes an automatic standby mode (see table 31, figure 18) whenever either chip enable is de-asserted (e1s =v ih or e2s=v il ). data retention the sram data retention performances as v dds go down to v dr are described in table 33 and fig- ure 23, 24. in e1s controlled data retention mode, minimum standby current mode is entered when e1s 3 v dds C 0.2v and e2s 0.2v or e2s 3 v dds C 0.2v. in e2s controlled data reten- tion mode, minimum standby current mode is en- tered when e2s 0.2v. output disable. the data outputs are high im- pedance when the output enable (gs )isatv ih with write enable (ws )atv ih .
23/46 m36dr432c, m36dr432d table 22. ac measurement conditions figure 5. ac measurement waveform note: v dd means v ddf =v dds figure 6. ac measurement load circuit table 23. device capacitance (1) (t a =25c,f=1mhz) note: 1. sampled only, not 100% tested. input rise and fall times 4ns input pulse voltages 0tov dd input and output timing ref. voltages v dd /2 ai90206 v dd 0v v dd /2 ai90207 c l = 50pf c l includes jig capacitance device under test 25k w v dd 25k w vdd 0.1f symbol parameter test condition min max unit c in input capacitance v in =0v 10 pf c out output capacitance v out =0v 12 pf
m36dr432c, m36dr432d 24/46 table 24. dc characteristics (t a = C40 to 85c; v ddf =v dds =1.9vto2.1v) symbol parameter device test condition min typ max unit i li input leakage current flash & sram 0v v in v dd 2 a i lo output leakage current flash & sram 0v v out v dd 10 a i dds v dd standby current flash ef =v ddf 0.2v v ddf =v dd max 15 50 a sram e1s 3 v dds C 0.2v, e2s v dds C 0.2v, v in 3 v dds C 0.2v or v in v dds C 0.2v, f=0 20 50 a i ddd supply current (reset) flash rpf =v ssf 0.2v 210a i dd supply current sram i io = 0 ma, e1s =v il , e2s = ws =v ih , v in =v il or v ih ,v dds =v dd max, cycle time = 1s 12ma i io = 0 ma, e1s =v il , e2s = ws =v ih , v in =v il or v ih ,v dds =v dd max, min cycle time 715ma i ddr supply current (read) flash ef =v il ,gf = v ih ,f=5mhz 10 20 ma i ddw supply current (program) flash program in progress 10 20 ma i ddwd supply current (dual bank) flash program/erase in progress in one bank read in the other bank 20 40 ma i dde supply current (erase) flash erase in progress 10 20 ma i ddes (1) supply current (erase suspend) flash erase suspend in progress 50 a i ddws (1) supply current (program suspend) flash program suspend in progress 50 a i pps program current (standby) flash v ppf v dds 0.2 5 a v ppf = 12v 0.6v 100 400 a i ppr program current (read) flash v ppf v dds 0.2 5 a v ppf = 12v 0.6v 100 400 a i ppw program current (program) flash v ppf = 12v 0.6v program in progress 510ma i ppe program current (erase) flash v ppf = 12v 0.6v program in progress 510ma v il input low voltage flash & sram C0.5 0.4 v v ih input high voltage flash & sram 1.4 v dd +0.2 v v ol output low voltage flash & sram v ddf =v dds =v dd min i ol = 100a 0.2 v v oh output high voltage flash & sram v ddf =v dds =v dd min i oh = C100a v dd C0.1 v
25/46 m36dr432c, m36dr432d note: 1. i ddes and i ddws are specified with device deselected. if device is read while in erase suspend, current draw is sum of i ddes and i ddr. if the device is read while in program suspend, current draw is the sum of i ddws and i ddr . table 25. flash read ac characteristics (ta = C40 to 85c; v ddf =1.9vto2.1v) note: 1. sampled only, not 100% tested. 2. gf may be delayed by up to t elqv -t glqv after the falling edge of ef without increasing t elqv v ppl program voltage (program or erase operations) flash 1.65 3.6 v v pph program voltage (program or erase operations) flash 11.4 12.6 v v pplk program voltage (program and erase lock-out) flash 1 v v lko v ddf supply voltage (program and erase lock- out) flash 2 v symbol alt parameter test condition flash unit 85 100 min max min max t avav t rc address valid to next address valid ef =v il ,gf =v il 85 100 ns t avqv t acc address valid to output valid (random) ef =v il ,gf =v il 85 100 ns t avqv1 t pa ge address valid to output valid (page) ef =v il ,gf =v il 35 45 ns t axqx t oh address transition to output transition ef =v il ,gf =v il 00ns t ehqx t oh chip enable high to output transition gf =v il 00ns t ehqz (1) t hz chip enable high to output hi-z gf =v il 25 35 ns t elqv (2) t ce chip enable low to output valid gf =v il 85 100 ns t elqx (1) t lz chip enable low to output transition gf =v il 00ns t ghqx t oh output enable high to output transition ef =v il 00ns t ghqz (1) t df output enable high to output hi-z ef =v il 25 35 ns t glqv (2) t oe output enable low to output valid ef =v il 25 35 ns t glqx (1) t olz output enable low to output transition ef =v il 00ns symbol parameter device test condition min typ max unit
m36dr432c, m36dr432d 26/46 figure 7. flash read ac waveforms ai90208 tavav tavqv taxqx telqx tehqx tglqv tglqx tghqx valid a0-a20 ef gf dq0-dq15 telqv valid tehqz tghqz note: write enable (w f ) = high.
27/46 m36dr432c, m36dr432d figure 8. flash page read ac waveforms ai90209 ef gf dq0-dq15 a2-a20 valid a0-a1 valid valid tehqx tghqz tghqx tehqz telqv tglqv tavqv valid valid valid valid valid valid tavqv1
m36dr432c, m36dr432d 28/46 table 26. flash write ac characteristics, write enable controlled (t a =C40to85c;v ddf = 1.9v to 2.1v note: 1. following a write cycle, if the next read is in the same bank as the write then t whgl is 30ns. figure 9. flash write ac waveforms, wf controlled note: 1. address are latched on the falling edge of wf , data is latched on the rising edge of wf . symbol alt parameter flash unit 85 100 min max min max t avav t wc address valid to next address valid 85 100 ns t avw l t as address valid to write enable low 0 0 ns t dvwh t ds input valid to write enable high 50 50 ns t elwl t cs chip enable low to write enable low 0 0 ns t ghwl output enable high to write enable low 0 0 ns t plq7v rpf low to reset complete during program/erase 15 15 s t vdhel t vcs v ddf high to chip enable low 50 50 s t whdx t dh write enable high to input transition 0 0 ns t wheh t ch write enable high to chip enable high 0 0 ns t whgl t oeh write enable high to output enable low 0 (1) 0 (1) ns t whwl t wph write enable high to write enable low 30 30 ns t wlax t ah write enable low to address transition 50 50 ns t wlwh t wp write enable low to write enable high 50 50 ns ai90210 ef gf wf a0-a20 dq0-dq15 valid valid v ddf tvdhel twheh twhwl telwl tavwl twhgl twlax twhdx tavav tdvwh twlwh tghwl
29/46 m36dr432c, m36dr432d table 27. flash write ac characteristics, chip enable controlled (t a = C40 to 85 c; v ddf =1.9vto2.1v) figure 10. flash write ac waveforms, ef controlled note: address are latched on the falling edge of ef ,dataislatchedontherisingedgeofef . symbol alt parameter flash unit 85 100 min max min max t avav t wc address valid to next address valid 85 100 ns t ave l t as address valid to chip enable low 0 0 ns t dveh t ds input valid to chip enable high 50 50 ns t ehdx t dh chip enable high to input transition 0 0 ns t ehel t cph chip enable high to chip enable low 30 30 ns t ehgl t oeh chip enable high to output enable low 30 30 ns t ehwh t wh chip enable high to write enable high 0 0 ns t elax t ah chip enable low to address transition 50 50 ns t eleh t cp chip enable low to chip enable high 50 50 ns t ghel output enable high chip enable low 0 0 ns t plq7v rpf low to reset complete during program/erase 15 15 s t vdhwl t vcs v ddf high to write enable low 50 50 s t wlel t ws write enable low to chip enable low 0 0 ns ai90211 ef gf wf a0-a20 dq0-dq15 valid valid v ddf tvdhwl tehwh tehel twlel tavel tehgl telax tehdx tavav tdveh teleh tghel
m36dr432c, m36dr432d 30/46 table 28. flash read and write ac characteristics, rpf related (t a = C40 to 85c; v ddf =1.9vto2.1v) figure 11. flash read and write ac waveforms, rpf related symbol alt parameter test condition flash unit 85 100 min max min max t phq7v1 rpf high to data valid (read mode) 150 150 ns t phq7v2 rpf high to data valid (power down enabled) 50 50 s t plph t rp rpf pulse width 100 100 ns t plq7v rpf low to reset complete during program/erase 15 15 s ai90212 dq7 wf rpf tplph tphq7v1,2 valid read dq7 valid tplq7v program / erase
31/46 m36dr432c, m36dr432d table 29. flash program, erase times and program, erase endurance cycles (t a = C40 to 85c; v ddf =1.9vto2.1v,v ppf =v ddf unless otherwise specified) note: 1. max values refer to the maximum time allowed by the internal algorithm before error bit is set. worst case conditions program or erase should perform significantly better. 2. excludes the time needed to execute the sequence for program instruction. table 30. flash data polling and toggle bits ac characteristics (1) (t a = C40 to 85 c; v ddf =1.9vto2.1v) note: 1. all other timings are defined in read ac characteristics table. parameter min max (1) ty p typical after 100k w/e cycles unit parameter block (4 kword) erase (preprogrammed) 2.5 0.15 0.4 s main block (32 kword) erase (preprogrammed) 10 1 3 s bank erase (preprogrammed, bank a) 2 6 s bank erase (preprogrammed, bank b) 10 30 s chip program (2) 20 25 s chip program (dpg, v pp = 12v) (2) 10 s word program 200 10 10 s program/erase cycles (per block) 100,000 cycles symbol parameter flash unit min max t ehq7v chip enable high to dq7 valid (program, ef controlled) 10 200 s chip enable high to dq7 valid (block erase, ef controlled) 1 10 s t ehqv chip enable high to output valid (program) 10 200 s chip enable high to output valid (block erase) 1 10 s t q7vqv q7 valid to output valid (data polling) 0 ns t whq7v write enable high to dq7 valid (program, wf controlled) 10 200 s write enable high to dq7 valid (block erase, wf controlled) 110s t whqv write enable high to output valid (program) 10 200 s write enable high to output valid (block erase) 1 10 s
m36dr432c, m36dr432d 32/46 figure 12. flash data polling dq7 ac waveforms ai90213 ef gf wf a0-a20 dq7 ignore valid dq0-dq6/ dq8-dq15 address (within blocks) tavqv tehq7v tglqv twhq7v valid tq7vqv dq7 data polling (last) cycle memory array read cycle data polling read cycles last write cycle of program or erase instruction telqv
33/46 m36dr432c, m36dr432d figure 13. flash data toggle dq6, dq2 ac waveforms ai90214 ef gf wf a0-a20 dq6,dq2 tavqv stop toggle last write cycle of program of erase instruction valid valid valid ignore data toggle read cycle memory array read cycle twhqv tehqv telqv tglqv data toggle read cycle dq0-dq1,dq3-dq5, dq7-dq15 note: all other timings are as a normal read cycle.
m36dr432c, m36dr432d 34/46 figure 14. flash data polling flowchart figure 15. flash data toggle flowchart read dq5 & dq7 at valid address start read dq7 fail pass ai90215 dq7 = data yes no yes no dq5 = 1 dq7 = data yes no read dq5 & dq6 start read dq6 fail pass ai90216 dq6 = toggles no no yes yes dq5 = 1 no yes dq6 = toggles
35/46 m36dr432c, m36dr432d table 31. sram read ac characteristics (t a = C40 to 85c; v dds =1.9vto2.1v) note: 1. sampled only. not 100% tested. figure 16. sram read mode ac waveforms, address controlled with ubs =lbs =v il note: e1s = low, e2s = high, gs =low,ws = high. symbol alt parameter sram unit min max t avav t rc read cycle time 85 ns t av qv t aa address valid to output valid 85 ns t axqx t oh address transition to output transition 10 ns t bhqz t bhz ubs , lbs disable to hi-z output 25 ns t blqv t ba ubs , lbs access time 45 ns t blqx t blz ubs , lbs enable to low-z output 5 ns t e1hqz t hz1 chip enable 1 high to output hi-z 25 ns t e1lqv t co1 chip enable 1 low to output valid 85 ns t e1lqx t lz1 chip enable 1 low to output transition 10 ns t e2hqv t co2 chip enable 2 high to output valid 85 ns t e2hqx t lz2 chip enable 2 high to output transition 10 ns t e2lqz t hz2 chip enable 2 low to output hi-z 25 ns t ghqz t ohz output enable high to output hi-z 25 ns t glqv t oe output enable low to output valid 45 ns t glqx t olz output enable low to output transition 5 ns t pd (1) chip enable 1 high or chip enable 2 low to power down 100 ns t pu (1) chip enable 1 low or chip enable 2 high to power up 0 ns ai90217 tavav tavqv taxqx a0-a17 dq0-dq15 valid data valid data valid
m36dr432c, m36dr432d 36/46 figure 17. sram read ac waveforms, e1s ,e2sorgs controlled note: write enable (ws )=high. figure 18. sram standby ac waveforms ai90218 tavav tavqv taxqx te1lqv te1lqx te1hqz tglqv tglqx tghqz data valid a0-a17 e1s gs dq0-dq15 te2hqv te2hqx valid te2lqz e2s tblqv tblqx tbhqz ubs, lbs ai90219 tpd e2s i dd tpu 50% e1s
37/46 m36dr432c, m36dr432d table 32. sram write ac characteristics (t a = C40 to 85c; v dds =1.9vto2.1v) note: 1. t as is measured from the address valid to the beginning of write. 2. t wr is measured from the end or write to the address change. t wr appliedincaseawriteendsase1s or ws going high. 3. t cw is measured from e1s going low end of write. 4. a write occurs during the overlap (t wp )oflowe1s and low ws . a write begins when e1s goes low and ws goes low with asserting ubs or lbs for single byte operation or simultaneously asserting ubs and lbs for double byte operation. a write ends at the ear- liest transition when e1s goes high and ws goes high. the t wp is measured from the beginning of write to the end of write. symbol alt parameter sram unit min max t avav t wc write cycle time 85 ns t av e1l t as (1) address valid to chip enable 1 low 0 ns t ave 2h t as (1) address valid to chip enable 2 high 0 ns t av wh t aw address valid to write enable high 75 ns t avwl t as (1) address valid to write enable low 0 ns t blwh t bw ubs , lbs valid to end of write 75 ns t dve1h t dw input valid to chip enable 1 high 45 ns t dve2l t dw input valid to chip enable 2 low 45 ns t dvwh t dw input valid to write enable high 45 ns t e1hax t wr (2) chip enable 1 high to address transition 0 ns t e1lwh , t e2hwh t cw (3) chip select to end of write 75 ns t e2lax t wr (2) chip enable 2 low to address transition 0 ns t ghqz t ghz output enable higt to output hi-z 25 ns t whax t wr (2) write enable high to address transition 0 ns t whdx t dh write enable high to input transition 0 ns t whqx t ow write enable high to output transition 5 ns t wlqz t whz write enable low to output hi-z 35 ns t wlwh t wp (4) write enable pulse width 65 ns
m36dr432c, m36dr432d 38/46 figure 19. sram write ac waveforms, ws controlled with gs low note: output enable (gs )=low. figure 20. sram write ac waveforms, ws controlled with gs high ai90220 tavav twhax tdvwh input valid a0-a17 e1s ws dq0-dq15 valid e2s tavwh tave2h twlwh tavwl twlqz twhdx twhqx tblwh ubs, lbs te2hwh tave1l te1lwh ai90221 tavav twhax tdvwh input valid a0-a17 e1s ws dq0-dq15 valid e2s tavwh tave2h twlwh tavwl twhdx twhqx tblwh ubs, lbs te2hwh tave1l te1lwh gs tghqz
39/46 m36dr432c, m36dr432d figure 21. sram write cycle waveform, ubs and lbs controlled figure 22. sram write ac waveforms, e1s controlled note: output enable (gs ) = high. ai90222 tavav te1hax tdvwh a0-a17 e1s ws dq0-dq15 valid e2s tavwh tavwl twhdx data valid tblwh ubs, lbs te1lwh te2hwh twlwh ai90223 tavav te1hax tdve1h a0-a17 e1s ws dq0-dq15 valid e2s tave1l tavwl twhdx input valid tblwh ubs, lbs te1lwh
m36dr432c, m36dr432d 40/46 table 33. sram low v dds data retention characteristics (1, 2) (t a = C40 to 85c; v dds =1.9vto2.1v) note: 1. all other inputs v ih v dd C0.2vorv il 0.2v. 2. sampled only. not 100% tested. figure 23. sram low v dds data retention ac waveforms, e1s controlled figure 24. sram low v dds data retention ac waveforms, e2s controlled symbol parameter test condition min max unit i dddr supply current (data retention) v dds = 1.2v, e1s 3 v dds C 0.2v, e2s 3 v dds C 0.2v or e2s 0.2v, f = 0 10 a v dr supply voltage (data retention) e1s 3 v dds C 0.2v, e2s 0.2v, f = 0 12.1v t cdr chip disable to power down e1s 3 v dds C 0.2v, e2s 0.2v, f = 0 0ns t r operation recovery time t rc ns ai90224 1.65 v e1s tcdr e1s 3 v dds C 0.2v 1.2 v v dr v sss v dds tr data retention mode ai90225 1.65 v e2s tcdr e2s 0.2v v dr v sss v dds tr data retention mode 0.4 v
41/46 m36dr432c, m36dr432d table 34. ordering information scheme devices are shipped from the factory with the memory content bits erased to 1. for a list of available op- tions (speed, package, etc...) or for further information on any aspect of this device, please contact the stmicroelectronics sales office nearest to you. table 35. daisy chain ordering scheme example: m36dr432c a 85 za 6 t device type m36 = mmp (flash + sram) architecture d = dual bank, page mode operating voltage r=v ddf =v dds =1.9v to 2.1v sram chip size & organization 4 = 4 mbit (256k x 16 bit) device function 32c = 32 mbit (x16), dual bank: 1/4-3/4 partitioning, top boot 32d = 32 mbit (x16), dual bank: 1/4-3/4 partitioning, bottom boot specification details a = flash: 0.25m; sram cypress 0.25m, supply 2v, speed 70ns speed 85 = 85ns 10 = 100ns package za = lfbga66: 0.8mm pitch temperature range 6=C40to85c option t = tape & reel packing example: m36dr432 -za t device type m36dr432 daisy chain -za = lfbga66: 0.8mm pitch option t = tape & reel packing
m36dr432c, m36dr432d 42/46 table 36. revision history date version revision details 20-sep-2001 -01 first issue 19-nov-2001 -02 lfbga66 mechanical data updated (table 37)
43/46 m36dr432c, m36dr432d table 37. stacked lfbga66 - 8 x 8 ball array, 0.8 mm pitch, package mechanical data figure 25. stacked lfbga66 - 8 x 8 ball array, 0.8 mm pitch, bottom view package outline note: drawing is not to scale. symbol millimeters inches typ min max typ min max a 1.400 0.0551 a1 0.250 0.0098 a2 1.100 0.0433 b 0.400 0.350 0.450 0.0157 0.0138 0.0177 d 12.000 C C 0.4724 C C d1 5.600 C C 0.2205 C C d2 8.800 C C 0.3465 C C ddd 0.100 0.0039 e 8.000 C C 0.3150 C C e1 5.600 C C 0.2205 C C e 0.800 C C 0.0315 C C fd 1.600 C C 0.0630 C C fe 1.200 C C 0.0472 C C sd 0.400 C C 0.0157 C C se 0.400 C C 0.0157 C C a2 a1 a bga-z12 ddd d e e b se fd fe e1 e d1 sd d2 ball "a1"
m36dr432c, m36dr432d 44/46 figure 26. stacked lfbga66 daisy chain - package connections (top view through package) ai90251 d c #4 #3 8 7 6 1 e f a b h g 5 4 3 2 #1 #2
45/46 m36dr432c, m36dr432d figure 27. stacked lfbga66 daisy chain - pcb connections proposal (top view through package) #1 ai90252 d c e f a b h g start point end point #4 #3 8 7 6 15 4 3 2 #2
m36dr432c, m36dr432d 46/46 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2001 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

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